High bandwidth interconnections between chips using conventional input/output (I/O) interfaces require significant power and chip area. Thus, in applications requiring significantly reduced power consumption and/or smaller chip area, these conventional I/O interfaces are not desirable.
Conventional I/O interfaces have limited configurability and scalability due, at least in part, to their significant power and chip area requirements.
Conventional I/O interfaces have physical layers that are designed and customized according to the requirements of the interface. Thus, conventional I/O interfaces having different configurations require different physical layer designs. Significant time and effort is required to customize the physical layer design for each different interface.